Modelling of Silicon-Based Quantum Computer Architecture

Quantum computers represent the next generation technology in computing and electronics. Through manipulation of quantum states, it will offer parallel processing power and capacity in applications of commercial and national significance. It is envisaged that a silicon based quantum computer will be realised by embedding phosphorus ion regularly in a lattice of pure silicon. The Centre for Quantum Computer Technology is focused on the fundamental physics and technology of fabricating a revolutionary silicon based solid state quantum computer prototype. Besides the fabrication of a Quantum bit ('Qubit'), computational modelling of the electrical behaviour of the Qubit is another important aspect of this project. Computational resources available at the APAC National Facility will be required to perform the complex calculations required to model and simulate the electrical behavour of a Qubit.

Principal Investigator

Kwan Lee
School of Electrical Engineering & Telecommunications
University of NSW

Project

f72

Co-Investigator

Andrew Dzurak
School of Electrical Engineering and Telecommunications
University of NSW

RFCD Codes

240203

Significant Achievements, Anticipated Outcomes and Future Work

We have been calculating the coupling capacitance between the various metallic gates on our nanoelectronic devices. Using the coupling capacitance information and an equivalent circuit model we have been able to examine the electrical behaviour of the devices. Primarily this has been focused on charge transfer characteristics and sensitivity of the Single Electron Transistors (SETs). We have applied the modelling to two devices that are being researched at the Centre for Quantum Computer Technology – metal double dot QC simulation devices (see image below) and Si:P double quantum dot devices.

Developing a ‘stable’ FASTCAP model has been an intensive process. However, once a ‘stable’ model has been created, the research has progressed well. We have been performing mainly perturbation analysis on the double dots to see how this affects the electrical behaviour of our devices. In the future we plan to change the geometry of our devices to understand how fabrication tolerance affects the electrical behaviour of the devices and use this information to optimise our design.

 

Computational Techniques Used

We run FASTCAP on the APAC National Facility AlphaServer SC, which is a freeware program that could be downloaded from Massachusetts Institute of Technology Computational Prototyping Group (http://www.rle.mit.edu/cpg/). FASTCAP is a multipole accelerated 3-D capacitance extraction program which can calculate the capacitance of arbitrary metallic objects.

Fundamentally capacitance between n conductors can be determined by raising the potential of one conductor to unity and grounding the remaining n-1 conductors. Capacitance between the grounded and the unity potential conductor is then the total charge on the grounded conductor (Q=CV). This is known as ‘direct evaluation’ and has a quadratic computational cost. Advantage offered by multipole expansion is realised when the panels are well separated – as it relies on approximating the far field contribution to the potential. The multipole coefficients used to approximate the potential need to be calculated only once – since the panels are ‘lumped’ as an equivalent charge at a far distance. FASTCAP has been implemented so that is uses multipole expansion only if the radius of the multipole region is less than half the distance between the centres.

FASTCAP has been used to calculate the capacitive coupling between the various surface gates and buried features in our nanoelectronic devices. Using this data we have been able to model the electrical data of our devices (charge transfer characteristics and device sensitivity) and compare with experimental results.

 

Publications, Awards and External Funding

External Funding and Awards

ARC Centre of Excellence Grant: “Centre for Quantum Computer Technology” R.G. Clark, G. J. Milburn, A. S. Dzurak, et. al.

US Army Research Office Grant: “Fabrication of a Solid State Quantum Computer” R.G. Clark, A. S. Dzurak, M. Y. Simmons, A. R. Hamilton & D. N. Jamieson

Publications

K. H. Lee, A. D. Greentree, V. Chan, T. M. Buehler, R. Brenner, A. S. Dzurak, A. R. Hamilton and R. G. Clark, “Robustness of Readout Devices for Si-based Quantum Computing”, Submitted to IEEE-NANO 2004 Conference.